With the rapid development of the internet technology, the internet television having internet interface is popularized gradually, user can browse the web, watch television and enjoy the movies, and so on, online on the television by inserting a cable in the television. However, when user uses a long cable outside (such as, the user interfaces a broadband network from neighbor to indoor), as too long cable is exposed to outdoor, when on a lightning day, lightning may induct the cable to produce large common-mode interference voltage and differential-mode interference voltage, the large common-mode interference voltage and the differential-mode interference voltage can affect, or even damage, a network signal processing chip in the internet interface circuit in the television, therefore affecting, or even damaging the network function of the television.
FIG. 1 is a circuit structure diagram of an existing internet interface circuit provided by an exemplary embodiment. Referring to FIG. 1, the internet interface circuit includes an ethernet interface 101, a first isolating transformer T11, a second isolating transformer T12, a network signal processing chip 102, a resistor R11, a resistor R12 and a capacitor C11. Wherein, the ethernet interface 101 is used for receiving and sending a network signal; the first isolating transformer T11 is used for separating a receiving data end of the ethernet interface 101 from the network signal receiving chip 102; the second isolating transformer T12 is used for separating a sending data end of the ethernet interface 101 from the network signal receiving chip 102; the network signal processing chip 102 is used for processing the network signal. In detail, a positive end RX+ of the receiving data end of the ethernet interface 101 is connected with a first end of a second primary coil of the first isolating transformer T11, a negative end RX− of the receiving data end of the ethernet interface 101 is connected with a first end of a first primary coil of the first isolating transformer T11; a second end of the first primary coil of the first isolating transformer T11 and a second end of the second primary coil of the first isolating transformer T11 are both connected with a first end of the capacitor C11 through the resistor R11; a second end of the capacitor C11 is earthed; a positive end TX+ of a sending data end of the ethernet interface 101 is connected with a first end of a fourth primary coil of the second isolating transformer T12, a negative end TX− of the sending data end of the ethernet interface 101 is connected with a first end of a third primary coil of the second isolating transformer T12; a second end of the third primary coil of the second isolating transformer T12 and a second end of a fourth primary coil of the second isolating transformer T12 are both connected with the first end of the capacitor C11 through the resistor R12; a first end of a secondary coil of the first isolating transformer T11 is connected with a receiving data negative end RX1− of the network signal processing chip 102, a second end of the secondary coil of the first isolating transformer T11 is connected with a receiving data positive end RX1+ of the network signal processing chip 102; a first end of a secondary coil of the second isolating transformer T12 is connected with a sending data negative end TX1− of the network signal processing chip 102, a second end of the secondary coil of the second isolating transformer T12 is connected with a sending data positive end TX1+ of the network signal processing chip 102. In addition, the receiving data negative end RX1− of the network signal processing chip 102 defines a static defending circuit 1021, the receiving data positive end RX1+ of the network signal processing chip 102 defines a static defending circuit 1022, the sending data positive end TX1+ of the network signal processing chip 102 defines a static defending circuit 1023, the sending data positive end TX1+ of the network signal processing chip 102 defines a static defending circuit 1024. Wherein, the static defending circuit 1021 includes a diode D11 and a diode D12 (the diode D11 and diode D12 are both diodes having very small stray capacitance). Wherein, a cathode of the diode D11 is connected with a working voltage input end VCC1 of the network signal processing chip 102, an anode of the diode D11 is connected with the receiving data negative end RX1− of the network signal processing chip 102 and a cathode of the diode D12 respectively; an anode of the diode D12 is earthed; the static defending circuit 1022 includes a diode D13 and a diode D14 (the diode D13 and diode D14 are both diodes having very small stray capacitance). Wherein, a cathode of the diode D13 is connected with the working voltage input end VCC1 of the network signal processing chip 102, an anode of the diode D13 is connected with the receiving data positive end RX1+ of the network signal processing chip 102 and a cathode of the diode D14 respectively; an anode of the diode D14 is earthed; the static defending circuit 1023 includes a diode D15 and a diode D16 (the diode D15 and diode D16 are both diodes having very small stray capacitance). Wherein, a cathode of the diode D15 is connected with the working voltage input end VCC1 of the network signal processing chip 102, an anode of the diode D15 is connected with the sending data negative end TX1− of the network signal processing chip 102 and a cathode of the diode D16 respectively; an anode of the diode D16 is earthed; the static defending circuit 1024 includes a diode D17 and a diode D18 (the diode D17 and diode D18 are both diodes having very small stray capacitance). Wherein, a cathode of the diode D17 is connected with the working voltage input end VCC1 of the network signal processing chip 102, an anode of the diode D17 is connected with the sending data positive end TX1+ of the network signal processing chip 102 and a cathode of the diode D18 respectively; an anode of the diode D18 is earthed.
Referring to FIG. 1, if when a common-mode interference voltage is applied to the signal cables of the positive end RX+ of the receiving data end, the negative end RX− of the receiving data end, the positive end TX+ of a sending data end, the negative end TX− of the sending data end of the ethernet interface 101, even the static defending circuit 1021, the static defending circuit 1022, the static defending circuit 1023, the static defending circuit 1024 in the network signal processing chip 102 have a certain defending effect against the common-mode interference voltage, but if the common-mode interference voltage is large enough, the large enough common-mode interference voltage can breakdown the first isolating transformer T11 and the second isolating transformer T12, then affect, even damage, the network signal processing chip 102, therefore affecting, even damaging, the network function of the television; supposing that the signal cable of the positive end RX+ of the receiving data end and the signal cable of the negative end RX− of the receiving data end of the ethernet interface 101 are interfered by differential-mode voltages which have opposite phases respectively, a large differential-mode current will occur between the two signal cables, the differential-mode current will flow from a primary side to a secondary side of the first isolating transformer T11, then affect, even damage, the network signal processing chip 102; similarly, if the signal cable of the positive end TX+ of the sending data end and the signal cable of the negative end TX− of the sending data end of the ethernet interface 101 are interfered by differential-mode voltages which have opposite phases respectively, another large differential-mode current will occur between the two signal cables, the differential-mode current will flow from a primary side to a secondary side of the second isolating transformer T12, also affect, even damage, the network signal processing chip 102, therefore affecting, even damaging, the network function of the television.